Method and apparatus for phostonic stack system for vehicle control/sense

ABSTRACT

An avionics system for a plane includes a plurality of nodes disposed throughout the plane, each node performing a function. The system includes an optical network in communication with the nodes and through which the nodes communicate. The system includes at least one of the nodes having a hardwired interpreter that interprets the information transmitted from another one of the nodes via the optical network. A method for operating a plane includes the steps of communicating information through an optical network between a plurality of nodes disposed throughout the plane, each node performing a function. There is the step of interpreting with at least one of the nodes having a hardwired interpreter the information transmitted from another one of the nodes via the optical network. A phostonic stack.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of U.S. patent application Ser. No. 11/647,828filed Dec. 28, 2006, which claims priority from U.S. provisional patentapplication Ser. No. 60/831,996 filed Jul. 19, 2006.

FIELD OF THE INVENTION

The present invention is related to the operation of a vehicle having anoptical network through which nodes that perform a function communicate.More specifically, the present invention is related to the operation ofa vehicle having an optical network through which nodes that perform afunction communicate where at least one of the nodes is a hardwiredinterpreter.

BACKGROUND OF THE INVENTION

Currently, the sensors and control of vehicles are mechanical links orelectrical wires. They may also be systems with microprocessors andsoftware to determine sensor input, relate the input, interpret thesensors for mean, min, and max for those sensors in order to givereadings and warnings. It uses the same technology to issue commands andcontrol to the vehicle. Some of these electrical links are analoginformation and yet other links are defined bus or interfacearchitectures. Many times, one must go through several adapters toconnect the correct information.

BRIEF SUMMARY OF THE INVENTION

The present invention pertains to an avionics system for a plane. Thesystem comprises a plurality of nodes disposed throughout the plane,each node performing a function. The system comprises an optical networkin communication with the nodes and through which the nodes communicate.The system comprises at least one of the nodes having a hardwiredinterpreter that interprets the information transmitted from another oneof the nodes via the optical network.

The present invention pertains to a method for operating a plane. Themethod comprises the steps of communicating information through anoptical network between a plurality of nodes disposed throughout theplane, each node performing a function. There is the step ofinterpreting with at least one of the nodes having a hardwiredinterpreter the information transmitted from another one of the nodesvia the optical network.

The present invention pertains to a phostonic stack interface system toa network. The stack comprises an FPGA. The stack comprises a Faradaycage, a driver for transferring information to the network, a photosensor to receive information from the network, a connector forcommunication to the network, and a power source to power the FPGA.

The present invention replaces current technology with a unique systemthat communicates through the entire vehicle's field replaceable units(FRUs). This is done through unique chip-to-chip optical links. Thislightens the equipment by eliminating devices and boxes as well asincrease security and removes vulnerability through photonics versuselectrical interfaces. The information is replicated in a unique methodof memory address links that are in update mode at all times.

Current technology uses an electrical interface or mechanical link torelay information about the vehicle as well as control the vehicle. Thecurrent technology may include a microprocessor, mechanical, and/orelectrical linked system. Most vehicles have a CPU that controls fuelmixtures, and monitors conditions to determine correct engine operationas well as provide warning information.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

In the accompanying drawings, the preferred embodiment of the inventionand preferred methods of practicing the invention are illustrated inwhich:

FIG. 1 shows various vehicles which utilize the system of the presentinvention.

FIG. 2 a shows a system of the present invention utilized with a drivecontrol and accelerator.

FIG. 2 b shows the system of the present invention utilized with acontrol wheel and throttle.

FIG. 3 is a block diagram of a hardwired interpreter of the presentinvention.

FIG. 4 a shows a portion of the system of the present invention utilizedwith a brake pedal.

FIG. 4 b shows a portion of the system of the present invention utilizedwith a yoke.

FIG. 5 a shows a portion of the system of the present invention utilizedwith a brake actuator.

FIG. 5 b shows a portion of the system of the present invention utilizedwith an elevator actuator.

FIG. 6 is a block diagram of the hardwired interpreter for a brake.

FIG. 7 shows an optical position sensor.

FIG. 8 shows a Faraday cage.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein like reference numerals refer tosimilar or identical parts throughout the several views, and morespecifically to FIG. 1 thereof, there is shown a control system 50 for avehicle 16. The system 50 comprises a plurality of nodes 52 disposedthroughout the vehicle 16, each node performing a function. The system50 comprises an optical network 54 in communication with the nodes 52and through which the nodes 52 communicate. The system 50 comprises atleast one of the nodes 52 having a hardwired interpreter 56 thatinterprets the information transmitted from another one of the nodes 52via the optical network 54.

Preferably, the hardwired interpreter 56 includes a dedicated circuitwithin a chip. The hardwired interpreter 56 preferably has no software.Preferably, the interpreter has no software. The interpreter preferablyincludes a local link to another one of the nodes associated with thehardwired interpreter. The hardwired interpreter preferably includes alink control in communication with the other nodes of the plurality ofnodes. Preferably, at least one of the other nodes is a sensor. Thevehicle is either a car, truck, bus, plane, train or boat and may bemanned or unmanned.

The present invention pertains to a method for operating a vehicle 16.The method comprises the steps of communicating information through anoptical network 54 between a plurality of nodes 52 disposed throughoutthe vehicle 16, each node performing a function. There is the step ofinterpreting with at least one of the nodes 52 having a hardwiredinterpreter 56 the information transmitted from another one of the nodes52 via the optical network 54.

The present invention pertains to a phostonic stack 58 interface system50 to a network 54. The stack 58 comprises an FPGA 74. The stack 58comprises a Faraday cage 76, a driver 78 for transferring information tothe network 54, a photo sensor to receive information from the network54, a connector for communication to the network, and a power source 80to power the FPGA 74.

In the past, control systems, such as in aircraft, were cables,hydraulics, and analog gauges to sensors for things like oil pressure,engine RPM, altitude, etc. As electronic circuits developed, theelectronics moved into the aircraft a little at a time with radios,electric tachometers, and now fly-by-wire. Computers control nearly allinformation transferred within an aircraft. New challenges have comeforward, such as lightning and aggressive disruptive electronic noisegeneration.

This invention replaces the existing cables with a plastic optical fiberthat connects all the systems in a vehicle 16, such as an aircraft. Inthe process of developing the optical links, the processor has beeneliminated and its latency by implementing hardwired state machines todo all of the control and monitor task done by processors previously.

The innovation of the phostonic stack 58 vehicle 16 control system 50is:

-   -   1) Eliminating the control harness.    -   2) Eliminating complex control interface.    -   3) Eliminate multiple adapters between standards.    -   4) Adding speed and reliability.    -   5) Linking sensors, control, and feedback with predetermined        allocated space.    -   6) Introducing the single device “floating” Faraday cage 76 for        integrity.    -   7) Eliminating mechanical linkages in many instances.    -   8) Reduction in overall maintenance cost.

This system 50 is based on taking the control interface and reducing thepossible commands to a series of memory locations that aresimultaneously updated at ˜1000 times a second throughout the vehicle16. The updates can be targeted to those units with a need to know, orupdate all of the units on the link.

See FIG. 1. It demonstrates the link between hardware, controls, andsensors 64. FIGS. 2 a and 2 b show the links are coherent. FIG. 3demonstrates a typical device layout using a Xilinx FPGA 74 that can bemade into an ASIC.

In FIG. 2 a, the sensors 64 for the drive control and the acceleratoralter the memory at the sending end, the information is sent to theother SCs on the link, and the units at those locations look at thememory address assigned to them and receive the updates.

In FIG. 2 b, the sensors 64 for the drive control and the acceleratoralter the memory at the sending end, the information is sent to theother SCs on the link, and the units at those locations look at thememory address assigned to them and receive the updates.

FIG. 3 is a representation of the Software-Less System with a visualsensation of the allocation on the device for its various components.This is merely a pictorial and may have no relationship to actuallocations.

Using the FPGA 74/ASIC in FIG. 3 eliminates the need for an operatingsystem and microprocessor. The functions of the microprocessor arereplicated in the ASIC VIA hardwired logic to perform the necessaryfunctions. All of the necessary information can be incorporated on asingle device, including both the local and link interface.

In FIG. 3, the local link 60 referred to at the top of the block is theMimic Memory interface to whatever device actually being talked with asopposed to the link control 62 which is the interface used to get databetween this device and the other equipment on the vehicle 16. Anexample of this interface is FireWire, IP, AFDX, etc. Any of theseinterface protocols can be used. Data is then sent on an internal bus tolocation either set in the device by default or by a state machinedirection. Many of the current systems know where they are by the plugat the location. The optical system 50 here can be operated in a similarfashion. The location can be either code by a mechanical indicator suchas a plug extension location on the surface provided of the “box” or byan optical sensor 64 on the device that reads a code for the location,or identifies an extrusion and its position to the connector.

The hardwired phostonic stack 58 system 50 is much faster as there is noinstruction load time and no lookup time involved in its operation.

Once a command is given with a microprocessor, if it is not in thesubroutines for the request, it must acquire the program or subroutine,execute it, and then issue the commands. This can take many, many clockcycles. With hardwired logic, it can only take as long as the longeststate sequence in this phostonic stack 58 solution.

Control has more information to cover urgency and priority of therequest and its interpretation. These can all be managed by thephostonic stack 58 solution, and updated through the IOI optical links.

The local link 60 referred to at the top of the block is the MimicMemory interface to the unit at this location. This “link” is defined bythe unit and may be from 1 to 128 bits wide. The link will be designedfor the unit or be logically assigned by the local interface statemachine.

If it is designed for a specific unit, the information received from theunit will be directly mapped to a local memory location. The informationto the unit will be sent directly from a memory location defined by thespecific detail for the unit attached.

If the unit is a logic assignment, the local interface state machine isimplemented. It can determine the unit by a code submitted from the unitat power up, a keyed local bus plug, an enquiry from the state machine,an assignment from another node, etc. It will then assign a memorylocation to link to for both to and from the unit.

This information to and from the memory locations reside in thePseudo-Memory Block. It is named pseudo-memory block as it may bememory, or temporary logic storage.

The main control state-machines have the function to do the operationsthat were preformed by the obsolete software and processors of the oldersystems. They take the information off the link control 62 and put it inthe correct local pseudo memory locations as well as take informationfrom the local memory and give it to the link control 62 for forwardingto the correct node. The main control is much faster than a processorfor two reasons, 1) there are no software cycles involved, and 2) thereis virtually no limit on the number of process being acted on in a trueparallel fashion.

The link control 62 sends and receives information off the node links.The node links are links between nodes 52, and at this time are currentstandards such as Ethernet/FireWire/10G-E/AFDX. While these are current,it does not exclude future links, some of which may be proprietary. Thelinked system 50 has its own buffer and repeater system to transfercurrent input to the output for doing its own add/drop function as wellas handling priority injection for emergencies.

Many of the current systems know where they are by the plug at thelocation. The present invention can be operated in a similar fashion.The location can be either code by a mechanical indicator such as a plugextension location on the surface provided of the “box” or by an opticalsensor 64 on the device that reads a code for the location, oridentifies an extrusion and it position to the connector. If it is to berouted by a state-machine, it will get the location from the incomingdata stream by doing a compare to see which locations in the “memory”the information should reside. This would be the case for nodes 52serving more than one local entity.

Operation:

The operation will be similar for all sensors and commands even thoughthe sensors will vary in type and style. The system 50 will accommodatelegacy equipment and sensors as well as drive legacy motors andactuators. This includes, but not limited to, Engine Control, EngineMonitors, Fuel Level, Fuel Tank Switching, Brake Control, Dash Lighting,Lights, Radio Links, Onboard Audio/Video Systems, and GPS, just to namea few.

As an example, a command from the brake pedal 66 to the brakes will befollowed.

In FIG. 4 a, the brake pedal 66 may be pushed to engage brakes. Thesensor 64 determines where the brake pedal 66 is located by the opticalsensors. It is given to the phostonic stack 58 module in terms of 100sor 1000ths of increment movement. It is monitored similar to themeasurements taken in a micrometer or vernier caliper, with theexception in this example, it is measured by optical refraction on theextension of the brake pedal 66 shaft.

When the shaft is moved, the digital number is sent to the phostonicstack 58 module. The phostonic stack 58 module is aware of the sendingdevice by the location of the connection on the bus and the type ofsensor/device. One method of defining the type of sensor/device is toground/short a combination of pins for the location. For example, pin 1and 5 of the 6 pin ID block that is the first 6 pins of the connector.Pins 12, 13, 14, 15, 16 could be input to the phostonic stack 58 modulefrom the brake pedal 66 sensor at the brake pedal 66.

The state machine in the SC is set to modify the locations in memory bythe ID block and locations of the data pins coming in. It will modifythe locations at 7000 through 7FFF.

The state machine in the Link Drive loop is directed to put the datafrom location 7000 to 7FFF on the link line to all the modules on thelink.

The module in FIG. 5 has loaded the data in its addresses 7000 to 7FFF.The local bus state machine's memory loaded bit is set and it reads thememory location and sends the data to the actuator as well as verifiesthe feedback of the physical location of the brake actuator.

The brake pistons 68 are moved appropriately. They in turn send afeedback signal to the back pressure unit on the brake pedal 66 arm,thus giving the impression the pedal is actually pushing a mechanicallinked brake pedal 66. This is accomplished through a small cylinderwith hydraulic fluid and a tiny control valve between chambers.

One method of the sensor 64 in FIG. 4 a is to use a hole or reflectorsin the shaft of the break pedal with optical drive and pickup for thesensor 64 operation. The holes or reflectors are located in such afashion as shown in FIG. 7. There is a total count of 128 positions inthis example. The presentation demonstrates triple redundancy for safetyin commercial vehicles.

As the reflector/hole plate travels horizontally, the light/sensor postdetermines how many of the 6 vertical positions “see” light and relatesthat information to the correct memory locations.

The information is saved here in FIG. 5 a from the sensors 64 in FIG. 4a to locations in the area for brake pressure/position. This is donethrough storing the information in the proper location in this sectionas specified in the manual for this vehicle 16. As this becomespractice, there may be an ideal location and increment for all vehicles.Location feedback may be handled by the same method as the brake sensor64.

In another example, a command from the yoke 70 to the elevator 72 in aplane is followed.

In FIG. 4 b, the yoke 70 may be moved to the right or left to change theelevator 72. The sensor 64 determines where the yoke 70 is located bythe optical sensors. It is given to the phostonic stack 58 module interms of 100s or 1000ths of increment movement. It is monitored similarto the measurements taken in a micrometer or vernier caliper, with theexception in this example, it is measured by optical refraction on theextension of the yoke 70 shaft.

When the shaft is moved, the digital number is sent to the phostonicstack 58 module. The phostonic stack 58 module is aware of the sendingdevice by the location of the connection on the bus and the type ofsensor/device. The type of sensor/device is grounded pin 1 and 5 of the6 pin ID block that is the first 6 pins of the connector. Pins 12, 13,14, 15, 16, and 17 are the input to the phostonic stack 58 module fromthe elevator 72 sensor 64 at the yoke 70.

The state machine in the SC is set to modify the locations in memory bythe ID block and locations of the data pins coming in. It will modifythe locations at 7000 through 7FFF.

The state machine in the Link Drive loop is directed to put the datafrom location 7000 to 7FFF on the link line to all the modules on thelink.

One method of the sensor 64 in FIG. 4 b is to use a hole or reflectorsin the shaft of the break pedal with optical drive and pickup for thesensor 64 operation. The holes or reflectors are located in such afashion as shown in FIG. 7. There is a total count of 128 positions inthis example. The presentation demonstrates triple redundancy for safetyin commercial vehicles.

As the reflector/hole plate travels horizontally, the light/sensor postdetermines how many of the 6 vertical positions “see” light and relatesthat information to the correct memory locations.

The module in FIG. 5 a has loaded the data in its addresses 7000 to7FFF. The local bus state machine's memory loaded bit is set and itreads the memory location and sends the data to the actuator as well asverify the feedback of the physical location of the elevator 72actuator.

The elevator 72 is moved appropriately.

The information is saved here in FIG. 5 b from the sensors 64 in FIG. 4b to locations in the area for brake pressure/position. This is donethrough storing the information in the proper location in this sectionas specified in the manual for this vehicle 16. As this becomespractice, there may be an ideal location and increment for all vehicles.Location feedback may be handled by the same method as the brake sensor64.

In another example, take the action of a turn signal:

For this example, assign the memory locations of 7000 to 7000F for theright turn signal and 70F0 for the left turn signal. This allows for a16 bit word to command the turn signal. Depending on the desiredcommand, it could be from “ON” to “ON with a timer”, etc. At this point,assume only turn on and turn off. Indicating a right turn throughdeflecting the turn signal lever or even a finger gesture for a righthand turn will change the local module that it is time to turn on theright turn signal. The actual signal from the actuator will set a localbit at 7001 to “ON”. The device senses this “memory change, reads thecontrol device memory locations to the interface, and transfers 16 bitsto the other memory devices on the network 54. The only receivers thatwill use these locations will be the turn indicators in each of the fourcorners of the car. These memory locations will sort the new informationand look at those locations to determine what to do. The front and rearexternal indicators will implement “ON” function as well as change thememory location at 7010 to a “1” to indicate the signal is on. If thesignal cannot come on due to a failure of some type, it will send anadditional bit (7011) to indicate it had received the command, but thereis trouble and rapidly flash the signal location at the instrument panelas well as record the information to the system memory for read out at agarage.

The Phostonic Stack 58 interface system 50 comprises at least one PLD orFPGA 74, a grounded or floating Faraday cage 76, at least one laserdriver 78 and at least one photo sensor (PIN), a connector(s), and atleast one photocell sheet. The PLD or FPGA 74 contains the logic andstate-machines to do the determinations, for sending and receivinginformation to both the network 54 and to the local unit. The Faradaycage 76 prevents erroneous electrical noise from entering or leaving theinternal circuits. The laser driver(s) 78 transfer information form thelocal unit to the network 54, and possibly to the local unit as well.The photo sensor(s) receive information generated by another node on thenetwork 54 and passed to this node via the network 54 and generate anelectrical pulse to be handled by the PLD or FPGA 74. The connector(s)contain the optical link to and from the network 54, as well as to andfrom the unit which can also be optical. The photocell sheet contains anumber of photocells to supply the PLD/FPGA 74 and lasers with enoughpower to function with a surplus to charge a storage device such as asuper cap that is designed to handle any interment shortcomings of thepower source 80. The number of photocells tied in series is defined bythe voltage needed by the devices; the number of series blocks inparallel is determined by the amount of power required by the devices atthis location.

There may be redundant FPGAs 74 as dictated by the governing agency suchas the DOT for land vehicles, Coast Guard for seaworthy craft, or FAAfor aircraft. The one encompassed here is a full duplex switchedEthernet, a MAC, and an I/O system to handle a local parallel memoryaddress capability. The Ethernet link will be through the laser and PIN.The photocell sheet will be powered by the light from a power source 80or the white light power system as described in U.S. patent applicationSer. No. ______, having attorney docket number VOGLEY-2 andcontemporaneously filed with this application. The photocell sheet isattached to the bottom of the FPGA 74 forming connections to the + and −of the FPGA 74. Since each photocell produces approximately 0.5 volts,the cells will be linked in series to produce 1.5 volts for the circuitsin the FPGA 74.

The floating Faraday cage 76 will completely encompass the FPGA 74,photocell sheet, and the I/O for external drive.

Xilinx, Altera, and Actel are manufacturers of FPGAs, with Actel leadingin radiation-hardened products. The triple redundancy allows forintegrity by continually checking all three paths for matchinginformation. If there is a difference, the two that match are consideredhaving the correct information and operation continues (this is called avoting system). Once each FPGA 74 is certified, the circuit can behardwired in an ASIC providing further integrity.

The system 50 is based on an FPGA 74 (Field Programmable Gate Array)that can be made into an ASIC (Application Specific Integrated Circuit)by the manufacturer. Once it is an ASIC, it can no longer be updated,hence the term “Hardwired”. During the initial phases, the FPGA 74 iscoded to respond to preferred protocol such as FireWire or IP. It isthrough this protocol that the FPGA 74 will communicate with its peers.

Each FPGA 74 will have hardwired state-machines that do the work of aprocessor. The state-machine operates on a series of operations at clockspeed. A state-machine can do a function, branch to anotherstate-machine, etc. For example:

-   -   1. State Machine Brake Control    -   2. Check brake feedback for entry—update console    -   3. Update counter    -   4. Check brake command entry—issue send update    -   5. Loop back to 1

All commands are similar to this scenario and step through the states ascommanded. When a change in the memory area is logged in the checkrequester, the state-machines can detect by a single bit check if itsarea has been changed and request the update to be posted whileresetting the register bit. This state-machine completes its cycle 7million times a second. Should it go a second without updating, anupdate will be forced. The second timeout is conditioned by the updatecounter overflow.

Also called “finite state machine,” it is a computing device designedwith the operational states required to solve a specific problem. Thecircuits are minimized, specialized and optimized for the application.For example, chips in audio, video and imaging controllers are oftendesigned as state machines, because they can provide faster performanceat lower cost than a general-purpose CPU. Automatic ticket dispensingmachines are another example. There are countless special-purposedevices built as state machines.

In order to conserve memory space, the device can be keyed by itslocation to use only the memory locations allocated for this locationand can be modified by an offset in the addressing register. Forexample, in FIG. 6, this location is actually starting at 1000, not7000. But the system 50 thinks it is at 7000 because that is where thebrake sensor 64 and control are located. The Loc key subtracts 6000 andtherefore starts the real location at 1000.

This is only necessary if after all state-machines are allocated, thereis not enough memory left to cover the need for all locations. The Lockey is needed to identify which state-machines to use as well as definethe memory allocations.

The local interface mimics SRAM memory in that it has an address bus anda data path to read in and read out of memory. This is described indetail within the Memory Mimic application. The I/O to the local entityis as a memory device. All sensors 64 send information to the memorydevice, and the entity reads from the memory device to acquireinstructions or commands. This information then gets shared with itspeers that record the information for their local interface to use.

All references to the link for this document have been centered on theIP or FireWire as they are the current standard interfaces for higherspeed interconnects. The protocol does not matter, this interface linkcould be any other protocol preferred by any vehicle manufacture.

FIG. 8 shows the inside of the Redundant(O) Box. It is not susceptibleto lightning and EMI due to non-electrical connections between insideand outside the box.

Although the invention has been described in detail in the foregoingembodiments for the purpose of illustration, it is to be understood thatsuch detail is solely for that purpose and that variations can be madetherein by those skilled in the art without departing from the spiritand scope of the invention except as it may be described by thefollowing claims.

1. A phostonic stack interface system to a network comprising: an FPGA;a floating Faraday cage; a driver for transferring information to thenetwork; a photo sensor to receive information from the network; aconnector for communication to the network; and a power source to powerthe FPGA.
 2. A method for operating a vehicle comprising the steps of:communicating information through an optical network between a pluralityof nodes disposed throughout the vehicle, each node performing afunction; and interpreting with at least one of the nodes theinformation transmitted from another one of the nodes via the opticalnetwork.
 3. A hardwired interpreter comprising: a local link; localinterface state machine in communication with the local link; apseudo-memory block in communication with the local interface statemachine; a main central state machine in communication with memoryblock; and a link control in communication with the main control statemachine.
 4. A control system for a vehicle comprising: a plurality ofnodes disposed throughout the vehicle, each node performing a function;an optical network in communication with the nodes and through which thenodes communicate; and at least one of the nodes having a hardwiredinterpreter that interprets the information transmitted from another oneof the nodes via the optical network.
 5. A system as described in claim4 wherein the hardwired interpreter includes a dedicated circuit withina chip.
 6. A system as described in claim 5 wherein the hardwiredinterpreter has no software.
 7. A system as described in claim 6 whereinthe hardwired interpreter includes a local link to another one of thenodes associated with the hardwired interpreter.
 8. A system asdescribed in claim 7 wherein the hardwired interpreter includes a linkcontrol in communication with the other nodes of the plurality of nodes.9. A system as described in claim 8 wherein at least one of the othernodes is a sensor.
 10. A system as described in claim 9 wherein thevehicle is either a car, truck, bus, plane, train or boat and may bemanned or unmanned.